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256k x 18 synchronous-pipelined cache tag ram cy7c1359a/gvt71256t18 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05120 rev. ** revised september 13, 2001 327 features ? fast match times: 3.5, 3.8, 4.0 and 4.5 ns fast clock speed: 166, 150, 133, and 100 mhz fast oe access times: 3.5, 3.8, 4.0 and 5.0 ns pipelined data comparator data input register load control by den optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3v ?5% and +10% core power supply 2.5v or 3.3v i/o supply 5v tolerant inputs except i/os clamp diodes to v ss at all inputs and outputs common data inputs and data outputs jtag boundary scan byte write enable and global write control three chip enables for depth expansion and address pipeline address, data, and control registers internally self-timed write cycle burst control pins (interleaved or linear burst se- quence) automatic power-down for portable applications low-profile jedec standard 100-pin tqfp package functional description the cypress synchronous burst sram family employs high-speed, low power cmos designs using advanced tri- ple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high valued resistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelin- ing chip enable (ce ), depth-expansion chip enables (ce 2 and ce 2 ), burst control inputs (adsc , adsp , and adv ), write enables (wel , weh , and bwe ), global write (gw ), and data input enable (den ). asynchronous inputs include the burst mode control (mode), the output enable (oe ) and the match output enable (moe ). the data outputs (q) and match output (match), enabled by oe and moe respectively, are also asynchronous. addresses and chip enables are registered with either ad- dress status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be inter- nally generated as controlled by the burst advance pin (adv ). data inputs are registered with data input enable (den ) and chip enable pins (ce , ce 2 , and ce 2 ). the outputs of the data input registers are compared with data in the memory array and a match signal is generated. the match output is gated into a pipeline register and released to the match output pin at the next rising edge of clock (clk). address, data inputs, and write controls are registered on-chip to initiate self-timed write cycle. write cycles can be one to two bytes wide as controlled by the write control inputs. in- dividual byte write allows individual byte to be written. wel controls dq1 ? dq9. weh controls dq10 ? dq18. wel and weh can be active only with bwe being low. gw being low causes all bytes to be written. the cy7c1359c/gvt71256t18 operates from a +3.3v pow- er supply with output power supply being +2.5v or +3.3v. all inputs and outputs are lvttl compatible. the device is ideally suited for address tag ram for up to 8 mb secondary cache. selection guide 7c1359a-166 71256t36-6 7c1359a-150 71256t36-6.7 7c1359a-133 71256t36-7.5 7c1359a-100 71256t36-10 maximum access time (ns) 3.5 3.8 4.0 4.5 maximum operating current (ma) 310 275 250 190 maximum cmos standby current (ma) 20 20 20 20
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 2 of 24 note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams f or detailed information. functional block diagram ? 256kx18 [1] dq dq weh# bwe# wel# gw# ce# ce2 ce2# higher byte write lower byte write output register oe# hi byte write adsp# adsc# address register binary counter & logic clr a a1-a0 adv# mode 256k x 9 x 2 sram array output buffers input register lo byte write dq1- dq18 dq dq dq enable power down logic zz dq latch den# compare dq moe# match clk latch 16
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 3 of 24 pin configurations 100-pin tqfp top view a nc nc v ccq v ssq nc dq9 dq8 dq7 v ssq v ccq dq6 dq5 v ss nc v cc zz dq4 dq3 v ccq v ssq dq2 dq1 nc nc v ssq v ccq match den moe nc nc nc v ccq v ssq nc nc dq10 dq11 v ssq v ccq dq12 dq13 v cc nc v ss dq14 dq15 v ccq v ssq dq16 dq17 dq18 nc v ssq v ccq nc nc nc a a ce ce 2 nc nc weh wel ce 2 v cc v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1359a/gvt71256t18 nc a a a a a1 a0 tms tdi v ss v cc tdo tck a a a a a a a mode 1234567 a v ccq a a adsp aav ccq b nc ce 2 aadsc ace 2 nc c nc a a v cc aanc d dq10 nc v ss nc v ss dq9 nc e nc dq11 v ss ce v ss nc dq8 f v ccq nc v ss oe v ss dq7 v ccq g nc dq12 weh adv v ss nc dq6 h dq13 nc v ss gw v ss dq5 nc j v ccq v cc nc v cc nc v cc v ccq k nc dq14 v ss clk v ss nc dq4 l dq15 nc v ss nc wel dq3 nc m v ccq dq16 v ss bwe v ss match v ccq n dq17 nc v ss a1 v ss dq2 den p nc dq18 v ss a0 v ss moe dq1 r nc a mode v cc nc a nc t nc a a nc a a zz u v ccq tms tdi tck tdo nc v ccq 119-lead bga top view
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 4 of 24 pin descriptions bga pins tqfp pins name type description 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 2t, 3t, 5t, 6t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set-up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle. 5l 3g 93 94 wel weh input- synchronous byte write enables: a byte write enable is low for a write cycle and high for a read cycle. wel controls dq1 ? dq9. weh controls dq10 ? dq18. data i/o are high impedance if either of these inputs are low, conditioned by bwe being low. 4m 87 bwe input- synchronous write enable: this active low input gates byte write opera- tions and must meet the set-up and hold times around the rising edge of clk. 4h 88 gw input- synchronous global write: this active low input allows a full 18-bit write to occur independent of the bwe and wen lines and must meet the set-up and hold times around the rising edge of clk. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip en- ables, write control, and data input enable control input on its rising edge. all synchronous inputs must meet set-up and hold times around the clock ? s rising edge. 4e 98 ce input- synchronous chip enable: this active low input is used to enable the device and to gate adsp . 6b 92 ce 2 input- synchronous chip enable: this active low input is used to enable the device. 2b 97 ce 2 input- synchronous chip enable: this active high input is used to enable the device. 4f 86 oe input output enable: this active low asynchronous input enables the data output drivers. 4g 83 adv input- synchronous address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 4a 84 adsp input- synchronous address status processor: this active low input, along with ce being low, causes a new external address to be regis- tered and a read cycle is initiated using the new address. 4b 85 adsc input- synchronous address status controller: this active low input causes de- vice to be deselected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. 3r 31 mode input- static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 7t 64 zz input- asynchronous snooze: this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc (no connect). 7n 52 den input- synchronous data input enable: this active low input is used to control the update of data input registers. 6m 53 match output match output: match will be high if data in the data input registers match the data stored in the memory array, assum- ing moe being low. match will be low if data do not match.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 5 of 24 notes: 2. x means ? don ? t care. ? h means logic high. l means logic low. it is assumed in this table that adsp is high and adsc is low. 3. e =l is defined as ce =low and ce 2 =low and ce 2 =high. e =h is defined as ce =high or ce 2 =high or ce 2 =low. we is defined as [bwe + wel *weh ]*gw . 4. all inputs except oe and moe must meet setup and hold times around the rising edge (low to high) of clk. 5. for a write operation following a read operation, oe must be high before the input data required setup time plus high-z time for oe and staying high throughout the input data hold time. 6. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 6p 51 moe input match output enable: this active low asynchronous input enables the match output drivers. 7p, 6n, 6l, 7k, 6h, 7g, 6f, 7e, 6d, 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 dq1 ? dq18 input/ output data inputs/outputs: input data must meet setup and hold times around the rising edge of clk. 5u 42 tdo output ieee 1149.1 test output. lvttl-level output. 2u 3u 4u 38 39 43 tms tdi tck input ieee 1149.1 test inputs. lvttl-level inputs. 4c, 2j, 4j, 6j, 4r 15, 41,65, 91 v cc supply power supply: +3.3v ? 5% and +10% 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground: gnd 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u 4, 11, 20, 27, 54, 61, 70, 77 v ccq i/o supply output buffer supply: +2.5v (from 2.375v to v cc ) 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 2n, 1p, 1r, 5r, 7r, 1t, 4t, 6u 1-3, 6, 7, 14, 16, 25, 28-30, 56, 57, 66, 75, 78, 79, 95, 96 nc - no connect: these signals are not internally connected. pin descriptions (continued) bga pins tqfp pins name type description burst address table (mode = nc/v cc ) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10 partial truth table for match [2, 3, 4, 5, 6] operation e we den moe oe match dq read cycle l h x x l - q write cycle lllxh-d fill write cycle l l h x h - high-z compare cycle l h l l h output d deselected cycle (match out) h x x l x h high-z deselected cycle h x x h x high-z high-z
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 6 of 24 notes: 7. x means ? don ? t care. ? h means logic high. l means logic low. write = l means [bwe + wel *weh ]*gw equals low. write = h means [bwe + wel *weh ]*gw equals high. it is assumed in this truth table that den is low. 8. wel enables write to dq1 ? dq9. weh enables write to dq10 ? dq18. 9. all inputs except oe must meet set-up and hold times around the rising edge (low to high) of clk. 10. suspending burst generates wait cycle. 11. adsp low along with chip being selected always initiates a read cycle at the l-h edge of clk. a write cycle can be performed by set ting write low for the clk l-h edge of the subsequent wait cycle. refer to write timing diagram for clarification. 12. x means ? don ? t care. ? h means logic high. l means logic low. it is assumed in this truth table that chip is selected and adsp is high along with den being low. truth table [5, 6, 7, 8, 9, 10, 11] operation address used ce ce2 ce2 adsp adsc adv write oe clk dq deselected cycle, power down none h x x x l x x x l-h high-z deselected cycle, power down none l x l l x x x x l-h high-z deselected cycle, power down none l h x l x x x x l-h high-z deselected cycle, power down none l x l h l x x x l-h high-z deselected cycle, power down none l h x h l x x x l-h high-z read cycle, begin burst external l l h l x x x l l-h q read cycle, begin burst external l l h l x x x h l-h high-z write cycle, begin burst external l l h h l x l x l-h d read cycle, begin burst external l l h h l x h l l-h q read cycle, begin burst external l l h h l x h h l-h high-z read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d partial truth table for read/write [12] function gw bwe weh wel read h h x x read h l h h write one byte h l l h write all bytes h l l l write all bytes l x x x
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 7 of 24 ieee 1149.1 serial boundary scan (jtag) overview this device incorporates a serial boundary scan access port (tap). this port is designed to operate in a manner consistent with ieee standard 1149.1-1990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modi- fied or eliminated because their implementation places extra delays in the critical speed path of the device. nevertheless, the device supports the standard tap controller architecture (the tap controller is the state machine that controls the tap ? s operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee stan- dard 1149.1 compliant taps. the tap operates using lvttl/lvcmos logic level signaling. disabling the jtag feature it is possible to use this device without using the jtag feature. to disable the tap controller without interfering with normal operation of the device, tck should be tied low (v ss ) to prevent clocking the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be pulled up to v cc through a resistor. tdo should be left unconnected. upon power-up the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) tck - test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms - test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. tdi - test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruc- tion that is currently loaded in the tap instruction register (re- fer to figure 1 , tap controller state diagram). it is allowable to leave this pin unconnected if it is not used in an application. the pin is pulled up internally, resulting in a logic high level. tdi is connected to the most significant bit (msb) of any reg- ister. (see figure 2 .) tdo - test data out (output) the tdo output pin is used to serially clock data-out from the registers. the output that is active depending on the state of the tap state machine (refer to figure 1 , tap controller state diagram). output changes in response to the falling edge of tck. this is the output side of the serial registers placed be- tween tdi and tdo. tdo is connected to the least significant bit (lsb) of any register. (see figure 2 .) performing a tap reset the tap circuitry does not have a reset pin (trst , which is optional in the ieee 1149.1 specification). a reset can be performed for the tap controller by forcing tms high (v cc ) for five rising edges of tck and pre-loads the instruction reg- ister with the idcode command. this type of reset does not affect the operation of the system logic. the reset affects test logic only. at power-up, the tap is reset internally to ensure that tdo is in a high-z state. test access port (tap) registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the tap ? s registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected, it is connected between the tdi and tdo pins. instruction register the instruction register holds the instructions that are execut- ed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruc- tion upon power-up or whenever the controller is placed in the test-logic reset state. when the tap controller is in the cap- ture-ir state, the two least significant bits of the serial instruc- tion register are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board-level serial test data path. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the device tap to another device in the scan chain with minimum delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional i/o pins (not counting the tap pins) on the device. this also includes a number of nc pins that are reserved for future needs. there are a total of 70 bits for a x36 device and 51 bits for a x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the device i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the con- troller is moved to shift-dr state. the extest, sample/ preload and sample-z instructions can be used to cap- ture the contents of the i/o ring. the boundary scan order table describes the order in which the bits are connected. the first column defines the bit ? s posi- tion in the boundary scan register. the msb of the register is connected to tdi, and lsb is connected to tdo. the second column is the signal name and the third column is the bump number. the third column is the tqfp pin number and the fourth column is the bga bump number.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 8 of 24 identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the device as described in the identification register definitions table. tap controller instruction set overview there are two classes of instructions defined in the ieee stan- dard 1149.1-1990; the standard (public) instructions and de- vice specific (private) instructions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the device or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, in- test, or the preload portion of the sample/preload com- mand. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the in- struction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction sets for this device are listed in the following tables. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this device. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the device responds as if a sample/preload instruction has been loaded. there is one difference between two instruc- tions. unlike sample/preload instruction, extest places the device outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in the instruction upon power-up and at any time the tap controller is placed in the test-logic reset state. sample-z if the high-z instruction is loaded in the instruction register, all output pins are forced to a high-z state and the boundary scan register is connected between tdi and tdo pins when the tap controller is in a shift-dr state. sample/preload sample/preload is an ieee 1149.1 mandatory instruction. the preload portion of the command is not implemented in this device, so the device tap controller is not fully ieee 1149.1-compliant. when the sample/preload instruction is loaded in the in- struction register and the tap controller is in the capture-dr state, a snap shot of the data in the device ? s input and i/o buffers is loaded into the boundary scan register. because the device system clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the input and i/o ring contents while the buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. to guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the tap controller ? s capture setup plus hold time (t cs plus t ch ). the device clock input(s) need not be paused for any other tap operation except capturing the input and i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the bound- ary scan register between the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction reg- ister has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap controller is in the shift-dr state, the bypass register is placed between tdi and tdo. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. reserved do not use these instructions. they are reserved for future use.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 9 of 24 note: 13. the 0/1 next to each state represents the value at tms at the rising edge of tck. figure 1. tap controller state diagram [13] test-logic reset reun-test/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 10 of 24 figure 2. tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tdi tdi [14] tap dc electrical characteristics (20 c < t j < 110 c; v cc = 3.3v ? 0.2v and +0.3v unless otherwise noted) parameter description test conditions min. max. unit v ih input high (logic 1) voltage [15, 16] 2.0 v cc + 0.3 v v il input low (logic 0) voltage [15, 16] ? 0.3 0.8 v il i input leakage current 0v < v in < v cc ? 5.0 5.0 a il o output leakage current output disabled, 0v < v in < v ccq ? 5.0 5.0 a v olc lvcmos output low voltage [15, 17] i olc = 100 a 0.2 v v ohc lvcmos output high voltage [15, 17] i ohc = 100 a v cc ? 0.2 v v olt lvttl output low voltage [15] i olt = 8.0 ma 0.4 v v oht lvttl output high voltage [15] i oht = 8.0 ma 2.4 v notes: 14. x = 53 for this device. 15. all voltage referenced to v ss (gnd). 16. overshoot: v ih (ac)< v cc + 1.5v for t< t khkh /2, undershoot: v il (ac)< ? 0.5v for t< t khkh /2, power-up: v ih < 3.6v and v cc < 3.135v and v ccq < 1.4v for t< 200 ms. during normal operation, v ccq must not exceed v cc . control input signals (such as gw , adsc , etc.) may not have pulse widths less than t khkl (min.). 17. this parameter is sampled.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 11 of 24 tap ac switching characteristics over the operating range [18, 19] parameter description min. max unit clock t thth clock cycle time 20 ns f tf clock frequency 50 mhz t thtl clock high time 8 ns t tlth clock low time 8 ns output times t tlqx tck low to tdo unknown 0 ns t tlqv tck low to tdo valid 10 ns t dvth tdi valid to tck high 5 ns t thdx tck high to tdi invalid 5 ns set-up times t mvth tms set-up 5 ns t cs capture set-up 5 ns hold times t thmx tms hold 5 ns t ch capture hold 5 ns notes: 18. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 19. test conditions are specified using the load in tap ac test conditions.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 12 of 24 tap timing and test conditions vt = 1.5v tdo z 0 = 50 ? figure 5 tap ac output load equivalent 50 ? 20 pf 3.0v v ss all input pulses 1.5v 1.0 ns 1.0 ns test clock (tck) t thth t thtl t tlth test mode select (tms) test data in (tdi) test data out (tdo) t mvth t thmx t dvth t thdx t tlqx t tlqv (a)
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 13 of 24 identification register definitions instruction field 512k x 18 description revision number (31:28) xxxx reserved for revision number. device depth (27:23) 00111 defines depth of 256k words. device width (22:18) 00011 defines width of x18 bits. reserved (17:12) xxxxxx reserved for future use. cypress jedec id code (11:1) 00011100100 allows unique identification of device vendor. id register presence indicator (0) 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 54 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. this instruction is not ieee 1149.1-compliant. idcode 001 preloads id register with vendor id code and places it between tdi and tdo. this instruction does not affect device operations. sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. reserved 011 do not use these instructions; they are reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this instruction does not affect device operations. this instruction does not implement ieee 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use these instructions; they are reserved for future use. reserved 110 do not use these instructions; they are reserved for future use. bypass 111 places the bypass register between tdi and tdo. this instruction does not affect device operations.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 14 of 24 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss .......... ? 0.5v to +4.6v v in .......................................................... ? 0.5v to v cc +0.5v storage temperature (plastic) ................... ? 55 c to +150 c junction temperature ............................................... +150 c power dissipation.......................................................... 1.0w short circuit output current........................................ 50 ma note: 20. t a is the case temperature. boundary scan order bit# signal name tqfp bump id 1a442r 2 a 45 2t 3 a 46 3t 4 a 47 5t 5a486r 6a493b 7a505b 8moe 51 6p 9den 52 7n 10 match 53 6m 11 dq1 58 7p 12 dq2 59 6n 13 dq3 62 6l 14 dq4 63 7k 15 zz 64 7t 16 dq5 68 6h 17 dq6 69 7g 18 dq7 72 6f 19 dq8 73 7e 20 dq9 74 6d 21 a 80 6t 22 a 81 6a 23 a 82 5a 24 adv 83 4g 25 adsp 84 4a 26 adsc 85 4b 27 oe 86 4f 28 bwe 87 4m 29 gw 88 4h 30 clk 89 4k 31 ce 2 92 6b 32 wel 93 5l 33 weh 94 3g 34 ce 2 97 2b 35 ce 98 4e 36 a 99 3a 37 a 100 2a 38 dq10 8 id 39 dq11 9 2e 40 dq12 12 2g 41 dq13 13 1h 42 nc 14 5r 43 dq14 18 2k 44 dq15 19 1l 45 dq16 22 2m 46 dq17 23 1n 47 dq18 24 2p 48 mode 31 3r 49 a 32 2c 50 a 33 3c 51 a 34 5c 52 a 35 6c 53 a1 36 4n 54 a0 37 4p operating range range ambient temperature [20] v cc com ? l 0 c to +70 c 3.3v ? 5%/+10% boundary scan order (continued) bit# signal name tqfp bump id
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 15 of 24 electrical characteristics over the operating range parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [15, 21] data inputs (dqxx) 1.7 v cc +0.3 v v ih all other inputs 1.7 4.6 v v il input low (logic 0) voltage [15, 21] ? 0.3 0.8 v il i input leakage current [22] 0v < v in < v cc ? 2 2 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 2 2 a v oh output high voltage [15, 23] i oh = ? 4.0 ma at v ccq = 3.135v 2.4 v v oh i oh = ? 4.0 ma at v ccq = 2.375v 1.7 v ol output low voltage [15, 23] i ol = 8.0 ma 0.4 v v cc supply voltage [15] 3.135 3.6 v v ccq i/o supply voltage [15] 2.375 v cc v parameter description conditions typ. 166 mhz/ -6 150 mhz/ -6.7 133 mhz/ -7.5 100 mhz/ -10 unit i cc power supply current: operating [24, 25, 26] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 100 310 275 250 190 ma i sb2 cmos standby [25, 26] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 5 10101010ma i sb3 ttl standby [25, 26] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 10 20 20 20 20 ma i sb4 clock running [25, 26] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 40 80 70 60 50 ma capacitance [17] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 4 5 pf c o input/output capacitance (dq) 7 8 pf thermal resistance description test conditions symbol bga typ. tqfp typ. unit thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer pcb ja 19 25 c/w thermal resistance (junction to case) jc 99 c/w note: 21. overshoot: v ih +6.0v for t t kc /2. undershoot:v il ? 2.0v for t t kc /2. 22. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of 3 0 a. 23. ac i/o curves are available upon request. 24. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 25. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 26. typical values are measured at 3.3v, 25 c, and 8.5-ns cycle time.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 16 of 24 ac test loads and waveforms (a) all input pulses 2.5v 0v 90% 10% 90% 10% 1.8 ns 1.8 ns (c) (b) vt = 1.25v 30 pf dq z 0 = 50 ? 50 ? dq +2.5v 1,667 ? 1,538 ? 5 pf (b) switching characteristics over the operating range [27] -6 166 mhz -6.7 150 mhz -7.5 133 mhz -10 100 mhz parameter description min. max. min. max. min. max. min. max. unit clock t kc clock cycle time 6.0 6.7 7.5 8.5 ns t kf clock frequency t kh clock high time 2.4 2.6 2.8 3.4 ns t kl clock low time 2.4 2.6 2.8 3.4 ns output times t kq clock to output valid 3.5 3.8 4.0 4.0 ns t km clock to match valid t kqx clock to output invalid 1.5 1.5 1.5 1.5 ns t kmx clock to match invalid t kqlz clock to output in low-z [17, 28, 29] 0 0 0 0 ns t kqhz clock to output in high-z [17, 28, 29] 1.5 6.0 1.5 6.7 1.5 7.5 1.5 8.5 ns t oeq oe to output valid [30] 3.5 3.5 3.8 3.8 ns t moem moe to match valid [30] t oelz oe to output in low-z [17, 28, 29] 0 0 0 0 ns t moelz moe to match in low-z [17, 28, 29] t oehz oe to output in high-z [17, 28, 29] 3.5 3.5 3.8 3.8 ns t moehz moe to match in high-z [17, 28, 29] set-up times t s address, controls, and data in [31] 1.5 1.5 1.5 2.0 ns hold times t h address, controls, and data in [31] 0.5 0.5 0.5 0.5 ns notes: 27. test conditions as specified with the output loading as shown in part (a) of ac test loads unless otherwise noted. 28. output loading is specified with c l = 5 pf as in ac test loads. 29. at any given temperature and voltage condition, t kqhz is less than t kqlz , t oehz is less than t oelz and t moehz is less than t moelz . 30. oe is a ? don ? t care ? after a write cycle begins to prevent bus contention, oe should be negated prior before the start of write cycle. 31. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table.
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 17 of 24 typical output buffer characteristics output high voltage pull-up current output low voltage pull-down current v oh (v) i oh (ma) min. i oh (ma) max. v ol (v) i ol (ma) min. i ol (ma) max. ? 0.5 ? 38 ? 105 ? 0.5 0 0 0 ? 38 ? 105 0 0 0 0.8 ? 38 ? 105 0.4 10 20 1.25 ? 26 ? 83 0.8 20 40 1.5 ? 20 ? 70 1.25 31 63 2.3 0 ? 30 1.6 40 80 2.7 0 ? 10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 18 of 24 switching waveforms read timing with burst feature [32, 33] notes: 32. ce active in this timing diagram means that all chip enables ce , ce 2 , and ce 2 are active. 33. in this timing diagram, it is assumed that den is tied to low (v ss ). clk adsp# adsc# address wel#, weh#, bwe#, gw# ce# adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) t kq t kqlz t oelz t kq t s t h t kh t kl t kc t oeq single read burst read t h t h t s t s t s
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 19 of 24 write timing with burst feature [32, 33] switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t h gw# a3 d(a1) d(a2+1) t kqx t oehz q d(a2+1) single write burst write burst write t h t h t s t s wel#, weh#, bwe#
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 20 of 24 read/write timing with burst feature [32, 33] switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) d(a5) d(a5+1) single write burst read burst write single reads a5 wel#, weh#, bwe#, gw#
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 21 of 24 read/write timing without burst feature [32, 34, 35] notes: 34. in this timing diagram, it is assumed that burst feature is not used and therefore adsp is tied to high (v cc ) and adsc is tied to low (v ss ). the logic state of adv is a ? don ? t care ? . 35. in this timing diagram, it is assumed that we = [bwe + wel *weh ]*gw . switching waveforms (continued) clk address we# ce# den# oe# dq a1 a2 a4 q(a1) q(a2) t s t h t kc a5 d(a5) d(a6) reads a8 a3 a6 a7 q(a3) q(a4) d(a7) d(a8) t kh t kl t kq t kqx t oehz t oeq t oelz t kqhz t kqlz writes
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 22 of 24 compare/fill write timing [32, 34, 35] switching waveforms (continued) clk address we# ce# den# oe# dq a1 t s t h t kc d(a1) t kh t kl t moelz t km moe# match a1 a2 d(a2) miss match high chip deselected fill write hit t moehz t moem t kmx
cy7c1359a/gvt71256t18 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ordering information speed (mhz) ordering code package name package type operating range 166 cy7c1359a-166ac/ gvt71256t18t-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial 150 cy7c1359a-150ac/ gvt71256t18t-6.7 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 133 cy7c1359a-133ac/ gvt71256t18t-7.5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 100 cy7c1359a-100ac/ gvt71256t18t-10 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1359a/gvt71256t18 document #: 38-05120 rev. ** page 24 of 24 document title: cy7c1359a/gvt71256t18 256k x 18 synchronous-pipelined cache tag ram document number: 38-05120 rev. ecn no. issue date orig. of change description of change ** 108311 09/25/01 bri new cypress spec ? converted from galvantech format

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